Table of Contents

1.1 Electronics and digital systems
1.2 Gates
1.3 Boolean algebra and equations
1.4 Digital circuit simulator
1.5 Timing diagrams
1.6 Equations to/from circuits
1.7 Basic circuit drawing conventions
1.8 Basic properties of Boolean algebra
1.9 Sum-of-products form
1.10 Binary and counting
1.11 Sum-of-minterms form
1.12 Truth tables
1.13 Product-of-sums form and maxterms
1.14 Top-down design + examples
1.15 Why study digital design
1.16 Multiple outputs

2.1 Two-level combinational logic simplification
2.2 K-maps: Introduction
2.3 3- and 4-variable K-maps
2.4 K-map examples
2.5 DeMorgan’s Law
2.6 XOR/XNOR gates
2.7 NAND/NOR (universal gates)
2.8 Muxes
2.9 Decoders
2.10 Encoders
2.11 Don’t cares
2.12 Prime implicants and minimal covers
2.13 Quine-McCluskey

3.1 SR latches
3.2 Clocks, D flip-flops, and registers
3.3 FSMs
3.4 FSM simulator
3.5 Capturing behavior with FSMs
3.6 FSM examples
3.7 FSMs to circuits (design)
3.8 Reducing states
3.9 State encodings
3.10 Mealy FSMs
3.11 FSM issues
3.12 Controller clock frequency
3.13 Circuits to FSMs (analysis)

4.1 Adders
4.2 Signed numbers in binary
4.3 Subtractors
4.4 Comparators
4.5 N-bit muxes
4.6 Load registers
4.7 Shifters
4.8 Counters and timers

5.1 HLSMs: Introduction
5.2 HLSMs with variables
5.3 HLSMs with a loop
5.4 HLSM simulator
5.5 Capturing behavior with HLSMs
5.6 Datapaths for HLSMs
5.7 HLSMs to circuits: RTL design
5.8 RTL timing
5.9 Assigning and reading variables

6.1 Tradeoffs
6.2 Carry-lookahead adders
6.3 Multipliers (array-style)
6.4 Register files
6.5 Multi-function registers
6.6 ALUs
6.7 SRAM and DRAM
6.8 RAM design
6.9 ROM design
6.10 Chip economics
6.11 Composing memory

7.1 Introduction to HDLs (Verilog)
7.2 Combinational logic (Verilog)
7.3 Identifiers (Verilog)
7.4 Testbench (Verilog)
7.5 Sequential logic (Verilog)
7.6 RTL design (Verilog)

8.1 Introduction to HDLs (VHDL)
8.2 Combinational logic (VHDL)
8.3 Identifiers
8.4 Testbench (VHDL)
8.5 Sequential logic
8.6 RTL design (VHDL)

9.1 ASCII and Unicode
9.2 Unsigned binary numbers
9.3 Signed binary numbers: Two’s complement
9.4 Binary, hexadecimal, and octal
9.5 General number bases
9.6 Floating-point numbers
9.7 Floating-point arithmetic
9.8 Arrays
9.9 Records
9.10 Graphics
9.11 Image and video data
9.12 Audio
9.13 Naming numerous bits

10.1 Gray code

What You’ll Find In This zyBook:

More action with less text.

  • Hundreds of participation activities: Questions, animations, tools
  • Exceptionally hands-on learning: Browser-based tools include algebraic solver, circuit simulator, K-map minimizer, state machine capture, high level state-machine capture, and more
  • Seamlessly integrated auto-generated and auto-graded challenge activities
  • Coverage emphasizes modern relevant approach, reaches RTL design in just 5 chapters
  • Ideal for traditional “what’s under the hood” goal, and for introduction to embedded systems

Instructors: Interested in evaluating this zyBook for your class? Sign up for a Free Trial and check out the first chapter of any zyBook today!

The zyBooks Approach

Less text doesn’t mean less learning.

An exceptionally hands-on approach to presenting digital design by combining theory and practice, including various web-based simulators, like a circuit simulator, finite-state machine simulator, high-level state machine simulator, datapath simulator, and more, plus numerous tools, like a Boolean algebra tool, a K-map minimizer tool, etc. The material emphasizes a top-down behavior-to-circuits approach, for combinational, sequential, and high-level (register-transfer-level) design. Emphasis is placed on RTL design, where most modern digital design occurs. This material’s HDL (Verilog and VHDL) coverage is intentionally template focused, teaching just enough of the HDLs to understand the templates.

“The most striking aspect of ZyBooks for me as an instructor has been the ability to introduce a topic and then point my students to specific exercises/activities in ZyBooks that would not only expound on the concept but allow them to practice them with confidence.”


Roman Lysecky
Professor of Electrical and Computer Engineering, Univ. of Arizona

Frank Vahid
Professor of Computer Science and Engineering, Univ. of California, Riverside