zyVersion - Computer Organization and Design (6e) - Interactive Version (RISC-V)

Table of Contents

1.1 Introduction
1.2 Seven great ideas in computer architecture
1.3 Below your program
1.4 Under the covers
1.5 Technologies for building processors and memory
1.6 Performance
1.7 The power wall
1.8 The sea change: The switch from uniprocessors to multiprocessors
1.9 Real stuff: Benchmarking the Intel Core i7
1.10 Going faster: Matrix multiply in Python
1.11 Fallacies and pitfalls
1.12 Concluding remarks
1.13 Historical perspective and further reading
1.14 Self study
1.15 Exercises

2.1 Introduction
2.2 Operations of the computer hardware
2.3 Operands of the computer hardware
2.4 Signed and unsigned numbers
2.5 Representing instructions in the computer
2.6 Logical operations
2.7 Instructions for making decisions
2.8 Supporting procedures in computer hardware
2.9 Communicating with people
2.10 RISC-V Addressing for Wide Immediates and Addresses
2.11 Parallelism and instructions: synchronization
2.12 Translating and starting a program
2.13 A C sort example to put it all together
2.14 Arrays versus pointers
2.15 Advanced material: Compiling C and interpreting Java
2.16 Real stuff: MIPS instructions
2.17 Real stuff: ARMv7 (32-bit) instructions
2.18 Real stuff: ARMv8 (64-bit) instruction set
2.19 Real stuff: x86 instructions
2.20 Real stuff: The rest of the RISC-V instruction set
2.21 Going faster: Matrix multiply in C
2.22 Fallacies and pitfalls
2.23 Concluding remarks
2.24 Historical perspective and further reading
2.25 Self study
2.26 Exercises
2.27 RISC-V Simulator

3.1 Introduction
3.2 Addition and subtraction
3.3 Multiplication
3.4 Division
3.5 Floating point
3.6 Parallelism and computer arithmetic: Subword parallelism
3.7 Real stuff: Streaming SIMD extensions and advanced vector extensions in x86
3.8 Going faster: Subword parallelism and matrix multiply
3.9 Fallacies and pitfalls
3.10 Concluding remarks
3.11 Historical perspective and further reading
3.12 Self study
3.13 Exercises

4.1 Introduction
4.2 Logic design conventions
4.3 Building a datapath
4.4 A simple implementation scheme
4.5 A multicycle implementation
4.6 An overview of pipelining
4.7 Pipelined datapath and control
4.8 Data hazards: Forwarding versus stalling
4.9 Control hazards
4.10 Exceptions
4.11 Parallelism via instructions
4.12 Putting it all together: The Intel Core i7 6700 and ARM Cortex-A53
4.13 Going faster: Instruction-level parallelism and matrix multiply
4.14 Advanced topic: An intro to digital design using a hardware design language to describe and model a pipeline
4.15 Fallacies and pitfalls
4.16 Concluding remarks
4.17 Historical perspective and further reading
4.18 Self study
4.19 Exercises

5.1 Introduction
5.2 Memory technologies
5.3 The basics of caches
5.4 Measuring and improving cache performance
5.5 Dependable memory hierarchy
5.6 Virtual machines
5.7 Virtual memory
5.8 A common framework for memory hierarchy
5.9 Using a finite-state machine to control a simple cache
5.10 Parallelism and memory hierarchies: Cache coherence
5.11 Parallelism and memory hierarchy: Redundant arrays of inexpensive disks
5.12 Advanced material: Implementing cache controllers
5.13 Real stuff: The ARM Cortex-A8 and Intel Core i7 memory hierarchies
5.14 Real stuff: The rest of the RISC-V system and special instructions
5.15 Going faster: Cache blocking and matrix multiply
5.16 Fallacies and pitfalls
5.17 Concluding remarks
5.18 Historical perspective and further reading
5.19 Self study
5.20 Exercises

6.1 Introduction
6.2 The difficulty of creating parallel processing programs
6.3 SISD, MIMD, SIMD, SPMD, and vector
6.4 Hardware multithreading
6.5 Multicore and other shared memory multiprocessors
6.6 Introduction to graphics processing units
6.7 Domain specific architectures
6.8 Clusters, warehouse scale computers, and other message-passing multiprocessors
6.9 Introduction to multiprocessor network topologies
6.10 Communicating to the outside world: Cluster networking
6.11 Multiprocessor benchmarks and performance models
6.12 Real stuff: Benchmarking the Google TPUv3 supercomputer and an NVIDIA Volta GPU cluster
6.13 Going faster: Multiple processors and matrix multiply
6.14 Fallacies and pitfalls
6.15 Concluding remarks
6.16 Historical perspective and further reading
6.17 Self study
6.18 Exercises

7.1 Introduction
7.2 Gates, truth tables, and logic equations
7.3 Combinational logic
7.4 Using a hardware description language
7.5 Constructing a basic arithmetic logic unit
7.6 Faster addition: Carry lookahead
7.7 Clocks
7.8 Memory elements: Flip-flops, latches, and registers
7.9 Memory elements: SRAMs and DRAMs
7.10 Finite-state machines
7.11 Timing methodologies
7.12 Field programmable devices
7.13 Concluding remarks
7.14 Exercises

8.1 Introduction
8.2 GPU system architectures
8.3 Programming GPUs
8.4 Multithreaded multiprocessor architecture
8.5 Parallel memory system
8.6 Floating point arithmetic
8.7 Real stuff: The NVIDIA GeForce 8800
8.8 Real stuff: Mapping applications to GPUs
8.9 Fallacies and pitfalls
8.10 Concluding remarks
8.11 Historical perspective and further reading

9.1 Introduction
9.2 Implementing combinational control units
9.3 Implementing finite-state machine control
9.4 Implementing the next-state function with a sequencer
9.5 Translating a microprogram to hardware
9.6 Concluding remarks
9.7 Exercises

10.1 Introduction
10.2 A survey of RISC architectures for desktop, server, and embedded computers
10.3 The Intel 80×86
10.4 The VAX architecture
10.5 The IBM 360/370 architecture for mainframe computers
10.6 Historical perspective and references

Authors

David A. Patterson
University of California, Berkeley

John L. Hennessy
Stanford University

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Based on the 2nd edition of Computer Organization and Design (COD) for RISC-V. As with other zyBooks, a key benefit of such interactivity is that students learn more and come to lecture more engaged when points are given for completing the interactive activities beforehand. This zyVersion includes:

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