Verilog, VHDL, and AI: Top 4 questions instructors asked about the new Digital Design zyLabs

When we opened up a live Q&A on the new Verilog and VHDL labs in Digital Design with zyLabs, the chat filled up fast. Instructors came with real classroom challenges, and the people who built the labs answered them directly.

Lab authors and instructors Jay Brockman and Todd DeLong joined Daniel Leung, our senior content author for labs and computer engineering, to walk through the platform. Here are the four questions instructors asked most, and what they learned.

1. Should I teach Verilog or VHDL?

Teach whichever one you prefer. This release includes seven Verilog labs and seven VHDL labs. Each pair covers the same content, so you can teach in either language without losing anything. You’ll find five labs per language in Chapter 2 (combinational logic) and two in Chapter 3 (sequential logic). We’ll add more as the content grows.

Jay explained how each language is used in industry today. “Verilog, specifically SystemVerilog, is probably where a lot of new designs start in industry today. VHDL is still very common in Department of Defense-oriented projects.” He started with VHDL himself before switching. “They both have their pros and cons. Once you know one, it’s not hard to pick up the other.”

What about SystemVerilog? SystemVerilog content is in development. You can already use it in labs you create yourself: the platform runs Icarus Verilog with SystemVerilog compiler settings, so you can write SystemVerilog code in any Verilog lab.

2. What stops students from pasting in AI-generated code?

This was the most direct question of the session. One instructor described what many face every day: a student copies the lab prompt into an AI tool, pastes the generated code back in, and gets a perfect score.

Jay didn’t downplay the problem. “Claude and ChatGPT and the others are pretty adept at hardware description languages these days,” he said. Introductory digital design has “no great secrets” about building a finite state machine or an arithmetic logic unit (ALU).

Here’s what zyLabs gives you to respond:

  • Student Behavior Insights. When students work in the zyLabs editor, the platform records their process and flags unusual patterns, such as a single paste of 700 characters right before submitting, very little time spent, or few test runs. You can replay a student’s full coding history to see how they reached their solution.
  • A tool for support, not punishment. Daniel was clear that the goal is “not promoting this tool as a police.” Behavior Insights also shows you students who are struggling. In one example, a student spent 43 minutes on a lab that usually takes 15 to 30, typed every line, and kept getting stuck at the same point. “If we can identify this student earlier, then we can reach out,” Daniel said. That kind of early outreach builds a learning environment where students are less likely to turn to AI first.
  • LockDown Browser for assessments. Homework is hard to control, but tests don’t have to be. LockDown Browser is available to all zyBooks instructors. You just turn it on for an assessment. Read the LockDown Browser guide or the zyBooks assessment guide, which includes a walkthrough video.

Tip: Behavior Insights works best when students do all their coding in the zyLabs editor, so make that a course requirement.

“It’s really tough to understand these concepts without being able to interact with real data, with real examples, with real algorithms.”

Aimee Schwab-McCoy, Director of Analytics and Content Authoring, zyBooks

3. I teach with breadboards or a schematic simulator. How does this fit?

Several instructors use breadboards, Multisim, CircuitVerse, or schematic-first tools like Digital. They wanted to know if zyLabs could support the same fundamentals.

zyLabs generates schematics from your code. Students write Verilog or VHDL, click Run, and open a schematic created from their design, so they can still see components connected by wires. They can also view signal timing in a built-in waveform viewer.

Jay has used every approach. He spent years teaching with 7400-series chips and breadboards, and he still uses a free schematic simulator for the introductory chapter. “Modern industrial design practice, though, is hardware description language-based,” he said. Here’s how his course works now:

  1. Students design and debug their circuits in the zyBook until every testbench passes.
  2. They export their Verilog or VHDL files as a zip file.
  3. They load the files into a vendor tool and program an FPGA board. Jay uses a Digilent board with an AMD/Xilinx chip.

“The zyBook is a much friendlier environment, quite honestly, than using some of these design tools right off the bat,” he said. Commercial tools can mean downloads of up to 70 GB that won’t run on a Mac or an older laptop. zyLabs runs a full Linux environment in the browser, with industry-standard open-source tools for simulation, schematic synthesis, and waveform viewing.

Todd sees the same benefit from the instructor side. “Right now, I’m dealing with prepping for people who are using a Mac, and who are using Windows, and who are using WSL under Windows, and it is just a logistical nightmare. This is just one prep.” One attendee who currently uses CircuitVerse put it simply: zyLabs is “much friendlier.”

4. How much can I customize the labs?

Instructors asked about template code, pacing, and whether the labs could challenge their strongest students. You have a lot of control:

  • Scaffolded starter code. Labs move through a series of parts. Early parts focus on exploring waveforms. Later parts give students partially working code with TODO comments to complete, such as a counter that counts up but still needs down-counting and an enable signal.
  • Readable testbenches. Our custom ZY_ASSERT_EQ macros take the signal to check, the expected result, and a message. They make testbenches easy for students to read and easy for you to write.
  • Clone and edit any lab. Clone a lab to make it yours, then change the specifications, template code, and model solution for each new semester. This is also a simple way to add harder problems for advanced students.
  • Decide who sees the solution. You can show or hide the model solution in each lab.
  • Control pacing. Unpublish sections so students can’t work ahead of your class, and reorder content to match your syllabus. “I do that all the time,” Jay said.
  • Build your own labs. Start from a blank lab or a provided one. We’ll walk you through the process in a one-on-one training session.

Grading is automatic. When students submit, built-in test cases grade their work, and scores sync to your zyBook assignments and your learning management system (LMS), such as Canvas.

What it looks like in class

The bigger story of the session was how these labs change class time. Jay assigns the zyBook reading first, then has students start the matching lab in class. “Let’s do parts one and two, and let’s leave parts three and four for the homework.”

Todd limits his lectures to 10 or 15 minutes, and students spend the rest of class working while he and his teaching assistants help. “I actually increase attendance because of this,” he said. “I have almost zero students show up for office hours. It makes your life as an instructor much easier.”

Explore the labs

The new Verilog and VHDL labs are included in Digital Design with zyLabs. You’ll find them at the end of Chapters 2 and 3, or you can filter for labs in the Content Explorer.

Have a question we didn’t cover? Reach out to your zyBooks account executive. We’re glad to set up another Q&A session.

See the Digital Design zyBook for yourself

Explore the animations, Verilog and VHDL zyLabs that make concepts click for your students. Request evaluation access to review the full book, or schedule a demo with a classroom learning solutions expert. Stay tuned for updates!

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