Digital Design
Frank Vahid
zyBooks 2018

Table of Contents

1. Combinational Logic
1.1 Electronics and digital systems
1.2 Gates
1.3 Boolean algebra and equations
1.4 Digital circuit simulator
1.5 Timing diagrams
1.6 Equations to/from circuits
1.7 Basic circuit drawing conventions
1.8 Basic properties of Boolean algebra
1.9 Sum-of-products form
1.10 Binary and counting
1.11 Sum-of-minterms form
1.12 Truth tables
1.13 Top-down design + examples
1.14 Why study digital design
1.15 Multiple outputs

2. Combinational Logic II
2.1 Two-level combinational logic simplification
2.2 K-maps: Introduction
2.3 3- and 4-variable K-maps
2.4 K-map examples
2.5 DeMorgan’s Law
2.6 XOR/XNOR gates
2.7 NAND/NOR (universal gates)
2.8 Muxes
2.9 Decoders
2.10 Don’t cares
2.11 Prime implicants and minimal covers
2.12 Quine-McCluskey

3. Sequential Logic
3.1 SR latches
3.2 Clocks, D flip-flops, and registers
3.3 FSMs
3.4 FSM simulator
3.5 Capturing behavior with FSMs
3.6 FSM examples
3.7 FSMs to circuits (design)
3.8 Reducing states
3.9 State encodings
3.10 Mealy FSMs
3.11 FSM issues
3.12 Controller clock frequency
3.13 Circuits to FSMs (analysis)

4. Datapath Components
4.1 Adders
4.2 Signed numbers in binary
4.3 Subtractors
4.4 Comparators
4.5 N-bit muxes
4.6 Load registers

5. RTL Design
5.1 HLSMs: Introduction
5.2 HLSMs with variables
5.3 HLSMs with a loop
5.4 HLSM simulator
5.5 Capturing behavior with HLSMs
5.6 Datapaths for HLSMs
5.7 HLSMs to circuits: RTL design
5.8 RTL timing
5.9 Assigning and reading variables

6. Datapath Components II
6.1 Tradeoffs
6.2 Carry-lookahead adders
6.3 Multipliers (array-style)
6.4 Register files
6.5 Multi-function registers
6.6 ALUs
6.7 SRAM and DRAM
6.8 RAM design
6.9 ROM design
6.10 Chip economics
6.11 Composing memory

7. Verilog HDL
7.1 Introduction to HDLs (Verilog)
7.2 Combinational logic (Verilog)
7.3 Identifiers (Verilog)
7.4 Testbench (Verilog)
7.5 Sequential logic (Verilog)
7.6 RTL design (Verilog)

8. VHDL
8.1 Introduction to HDLs (VHDL)
8.2 Combinational logic (VHDL)
8.3 Identifiers
8.4 Testbench (VHDL)
8.5 Sequential logic
8.6 RTL design (VHDL)

9. Appendix: Information as Bits
9.1 ASCII and Unicode
9.2 Unsigned binary numbers
9.3 Signed binary numbers: Two’s complement
9.4 Binary, hexadecimal, and octal
9.5 General number bases
9.6 Floating-point numbers
9.7 Floating-point arithmetic
9.8 Arrays
9.9 Records
9.10 Graphics
9.11 Image and video data
9.12 Audio
9.13 Naming numerous bits

10. Additional Material
10.1 Gray code