Digital Design
Frank Vahid
zyBooks 2017

1. Combinational Logic
1.1 Voltage and current
1.2 Switches
1.3 CMOS transistors
1.4 Transistors and gates
1.5 Boolean algebra
1.6 Boolean algebra and digital design
1.7 Digital circuit simulator
1.8 Timing diagrams
1.9 Equations to/from circuits
1.10 Basic properties of Boolean algebra
1.11 Sum-of-products form for circuits
1.12 Binary and counting
1.13 Sum-of-minterms form
1.14 Truth tables
1.15 Why study digital design
1.16 Basic circuit drawing conventions

2. Combinational Logic II
2.1 Two-level combinational logic minimization
2.2 K-maps: Introduction
2.3 More K-maps
2.4 More Boolean algebra: DeMorgan’s Law
2.5 XOR and XNOR gates
2.6 Universal gates
2.7 Muxes
2.8 Decoders
2.9 Don’t cares
2.10 Prime implicants
2.11 Quine-McCluskey

3. Sequential Logic
3.1 SR latches
3.2 Flip-flops
3.3 Basic registers
3.4 FSMs
3.5 FSM simulator
3.6 Capturing behavior with FSMs
3.7 FSMs to circuits
3.8 Circuits to FSMs
3.9 Reducing states
3.10 State encodings
3.11 Mealy FSMs
3.12 FSM issues
3.13 Controller clock frequency

4. Datapath Components
4.2 Signed numbers in binary
4.3 Subtractors
4.4 Comparators
4.5 N-bit muxes

5. RTL Design
5.1 HLSMs: Introduction
5.2 HLSMs with variables
5.3 HLSMs with a loop
5.4 HLSM simulator
5.5 Capturing behavior with HLSMs
5.6 Datapaths for HLSMs
5.7 HLSMs to circuits: RTL design
5.8 RTL timing

6. Datapath Components II
6.3 Multipliers (array-style)
6.4 Register files
6.5 Multi-function registers
6.6 ALUs
6.7 SRAM and DRAM
6.8 RAM design
6.9 ROM design
6.10 Chip economics
6.11 Composing memory

7. Verilog HDL
7.1 Introduction to HDLs (Verilog)
7.2 Combinational logic (Verilog)
7.3 Identifiers (Verilog)
7.4 Testbench (Verilog)
7.5 Sequential logic (Verilog)
7.6 RTL design (Verilog)

8. VHDL
8.1 Introduction to HDLs (VHDL)
8.2 Combinational logic (VHDL)
8.3 Identifiers
8.4 Testbench (VHDL)
8.5 Sequential logic
8.6 RTL design (VHDL)

9. Appendix: Information as Bits
9.1 ASCII and Unicode
9.2 Unsigned binary numbers
9.3 Signed binary numbers: Two’s complement